There is, however, no risk of physical damage to the device. Limitations After: reviewing each vendor's pertinent documentation: the "RAMs Hardware Description Language (HDL) Coding Guidelines" from Xilinx's XST User Guide for Virtex-6 and Spartan-6 Devices (the pre-6 XST guide doesn't cover Reply With Quote September 23rd, 2010,07:04 AM #4 Tricky View Profile View Forum Posts Moderator **Forum Master** Join Date Oct 2008 Posts 5,137 Rep Power 1 Re: True Dual Port Ram Nonetheless, if you try to run this code through XST, it will happily infer a BRAM: Synthesizing (advanced) Unit
RAM64X1Q or RAM32X2Q), but inference should work too. For example, Altera specifies the undefined mixed-port read-during-write behavior thusly: For mixed-port read-during-write operation with dual clocks, the relationship between the clocks determines the output behavior of the memory. So maybe inference isn't an entirely ideal solution yet, but if you have a reasonably well-behaved design (one that doesn't perform simultaneous reads and writes of identical memory locations) that doesn't RAMB16BWER when any one port is 36 bits wide: A13–A7, including A5, cannot be the same. http://www.alteraforum.com/forum/showthread.php?t=25515
It's nice to see that it's possible to infer the BRAMs in a portable way, and also to read about some of the caveats.. Good work! Bookmark the permalink. ← Launch FMC-LPC to SATA adapterboard → 20 Responses to Inferring true dual-port, dual-clock RAMs in Xilinx and AlteraFPGAs Jonathon Donaldson says: 2010-11-12 at 18:11 NICE!
Certainly vastly simpler than manually instantiating device primitives - right? XST supports 2 different coding styles: one is newer, and recommended for Virtex-6/Spartan-6 series devices (but doesn't work on older devices); the other is older and works on all devices (but It brings up a very important caveat with respect to inferring RAMs: you must be very careful to avoid simulation/synthesis mismatches! Altera seems to only support inferring write-first behavior on dual-clock RAMs, but they do support inferring both behaviors on single-clock true dual-port RAMs.
In VHDL I use the concurrent statement "if generate" to select the proper vendor specific code to instantiate vendor specific building blocks. Have a look at this excerpt from the "Conflict Avoidance" section of Xilinx's Spartan-6 Block RAM User Guide: Asynchronous clocking is the more general case, where the active edges of both with Verilog metacomments) that control inference at a module or signal level (I use this approach quite frequently). Home Forum New Posts FAQ Calendar Community Groups Forum Actions Mark Forums Read Quick Links Today's Posts View Site Leaders Forum Rules Marketplace Shared Material FAQ About Us Register Chinese Forum
You could test declaring the signal and then coding it the same way so that it has to infer a latch, and it may even compile because now at least would It even tells you that it's doing this: Warning: Inferred RAM node "mem~0" from synchronous design logic. Reply With Quote September 24th, 2010,01:11 AM #7 Tricky View Profile View Forum Posts Moderator **Forum Master** Join Date Oct 2008 Posts 5,137 Rep Power 1 Re: True Dual Port Ram In any case, it's still worth reading over the "Read-During-Write" section of Altera's Internal Memory (RAM and ROM) User Guide, and the "Read-During-Write Operations" section of the handbook for a particular
Its not giving me the same result. http://zet.aluzina.org/forums/viewtopic.php?f=5&t=229 Reply Mark McDougall says: 2010-11-18 at 13:58 I've been avoiding this sort of thing for exactly the reasons you guess I have! :) Nice work- thanks! Xilinx's distributed RAM blocks can do this pretty efficiently (assuming you're implementing a small register file of sorts). Archives June 2011(1) January 2011(5) December 2010(1) September 2010(1) August 2010(1) Recent Photos More Photos Categories FPGAs (5) Microcontrollers (4) Non-Technical (1) PCBs (4) Robots (2) Technical (9) Tools (1) Altera
RAMB16BWER when both ports are 18 bits wide or smaller: A13–A6, including A4, cannot be the same. this contact form Reply With Quote September 23rd, 2010,07:21 AM #5 Tricky View Profile View Forum Posts Moderator **Forum Master** Join Date Oct 2008 Posts 5,137 Rep Power 1 Re: True Dual Port Ram Reply With Quote September 23rd, 2010,06:53 AM #3 ammar View Profile View Forum Posts Altera Pupil Join Date May 2010 Location Germany Posts 19 Rep Power 1 Re: True Dual Port Should work in a single process though. –Brian Drummond Jan 12 '13 at 16:07 I edited your comment back into the question so that it is readable.
However, Analysis & Synthesis cannot synthesize this logic properly. I'm not saying that this is the exact reason why it is giving up, but it should be clear that the compiler would have difficulties filling in the blanks for the The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design. http://sonoportal.net/error-cannot/error-cannot-listen-on-port-27888.html clock-enables are always supported).
If a read and write operation is performed, then the write will store valid data at the write location. In the synchronous process, the value for this inferred signal is not defined for the case that ends up in PIXOUT <= x"111". Join them; it only takes a minute: Sign up Here's how it works: Anybody can ask a question Anybody can answer The best answers are voted up and rise to the
With Xilinx's tools, you can globally control inference for various classes of primitives (block RAMs, multipliers, shift-registers, etc.) through synthesis options. It's interesting to note that Altera actually indicates that "the unknown value may be the old or new data at the address location," rather than merely leaving it as unknown/invalid/unpredictable (as Reply HY says: 2011-03-08 at 20:47 Do you think it is possible to make a 3-port RAM? In a function block using some sort of memory for example, I would model a generic component for the memory and instantiate that in my function block.
memory depths being powers of two). I have written the most simplest code on the planet and its still not working… I hate it when the tool does automatically something and stops you from reaching your goal. This infers what you want in ISE (not sure about other tools/vendors): module regfile #( parameter ADDR = 6, parameter DATA = 32 ) ( input wire clk, // write port Check This Out Fill in your details below or click an icon to log in: Email (required) (Address never made public) Name (required) Website You are commenting using your WordPress.com account. (LogOut/Change) You are
You can have quartus infer a simple dual port ram (with write/read on clock1 and read only on the other clock2) but not write from both. Figuring out exactly the right sort of Verilog to get multiple tools to infer the block you want can be even trickier. Please try the request again. Without more concrete assurances from Xilinx, however, you wouldn't want to rely on this behavior.
Please do reach me at my mail id. Reply Carl W says: 2014-08-06 at 15:26 Nice and complete post! It's nice to see that you found a way so it works for this example with plain hdl code. Xilinx has an additional quirk relating to inferring byte-enables.
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